https://scholars.lib.ntu.edu.tw/handle/123456789/607350
標題: | Improved switching time in negative capacitance junctionless transistors | 作者: | Gupta M VITA PI-HO HU |
關鍵字: | Capacitance;Drain current;Logic design;Switching;Transistors;VLSI circuits;Device parameters;Gate length;Gate work function;Inversion modes;Junctionless transistors;Negative capacitance;Switching time;Computer circuits | 公開日期: | 2021 | 來源出版物: | VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings | 摘要: | This work investigates the switching time in negative capacitance (NC) junctionless (JL) and inversion mode (IM) transistors through calibrated simulations. Results highlight that NCJL devices designed with an optimal underlap of 6 nm and appropriate gate work-function achieve a higher effective drain current than NCIM transistors. Our results show that a higher effective drain current improves the switching time in NCJL devices at a shorter gate length of 14 nm. Besides, the impact of device parameters on the switching time of NCJL and NCIM devices is analyzed. Results reported for the first time provide new viewpoints on designing logic circuits using NCJL transistors with improved switching time. ? 2021 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85108151904&doi=10.1109%2fVLSI-TSA51926.2021.9440137&partnerID=40&md5=b652ae62abdb6d471dcf8206c3299090 https://scholars.lib.ntu.edu.tw/handle/123456789/607350 |
DOI: | 10.1109/VLSI-TSA51926.2021.9440137 |
顯示於: | 電機工程學系 |
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