Monolithic 3D SRAM cell with stacked two-dimensional materials based FETs at 2nm node
Journal
Proceedings - IEEE International Symposium on Circuits and Systems
Journal Volume
2021-May
Date Issued
2021
Author(s)
Abstract
Continued scaling of the interconnect geometry increases the metal resistance which degrades the performance of SRAM in advanced technology nodes. We propose an energy-efficient multi-tiers monolithic 3D (M3D) SRAM cell design with stacked 2D material nanosheet FETs to release the impact of metal line resistance. Considering the 2nm node design rules, the 3-tier M3D SRAM cell with stacked MoS2 FETs shows a 42% reduction in cell area, 49% improvement in read access time, and 68% improvement in energy-delay product. The energy- and area-efficient high-performance 3-tier M3D SRAM cell enables intelligent functionalities for the area and energy-constrained edge computing devices. ? 2021 IEEE
Subjects
2-D material
Area efficiency
Energy efficiency
Monolithic 3-D (M3D)
SRAM
Cells
Cytology
Layered semiconductors
Molybdenum compounds
Advanced technology
Computing devices
Energy delay product
Energy efficient
Energy-constrained
Interconnect geometry
Metal resistances
Two-dimensional materials
Integrated circuit design
SDGs
Type
conference paper