An Ultra-Low Latency 7.8-13.6 pJ/b Reconfigurable Neural Network-Assisted Polar Decoder with Multi-Code Length Support
Journal
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Journal Volume
2020-June
ISBN
9.78173E+12
Date Issued
2020
Author(s)
DOI
85PXA
Abstract
To meet with the stringent requirements of ultra-low latency communication in 5G, this work presents a polar decoder fabricated in TSMC 40nm CMOS featuring: 1) World's first neural network-assisted decoder chip with 8× improvement of convergence rate. 2) Fully reconfigurable architecture to support multi-code length operations with a 2-to-8× hardware utilization rate. 3) Optimized fixed-point design of processing element (PE) to reduce 73% area and 67% power consumption. © 2020 IEEE.
SDGs
Other Subjects
5G mobile communication systems; Decoding; Network coding; Reconfigurable architectures; VLSI circuits; Convergence rates; Fixed points; Hardware utilization; Low latency; Low-latency communication; Processing elements; Reconfigurable; Stringent requirement; Neural networks
Type
conference paper