A Fully Integrated 1.7mW Attention-Based Automatic Speech Recognition Processor
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
69
Journal Issue
10
Pages
4178
Date Issued
2022-10-01
Author(s)
Abstract
This brief presents a low-power attention-based automatic speech recognition (ASR) processor achieving real-time recognition capability. The proposed attention window algorithm, compact end-to-end neural-network topology, and efficient computation dataflow effectively minimize the hardware complexity and power consumption, enabling a fully integrated low-power ASR processor solution without the necessity of any off-chip memory resource. The proposed design techniques reduced 98.9% weight memory and 92.1% power consumption with minimal degradation of 2.24% in recognition accuracy. The proposed ASR processor operates at 100MHz with 1.7mW at 0.9V, demonstrating 2x and 1.68x performance improvements in speed and power, respectively, compared to the previous ASR designs that require additional supports of off-chip memory or external decoder.
Subjects
attention mechanism | automatic speech recognition | CMOS digital integrated circuits | energy-efficient | low-power | neural network (NN)
SDGs
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Type
journal article