https://scholars.lib.ntu.edu.tw/handle/123456789/632293
標題: | Sensitivity Analysis of Ferroelectric Junctionless Transistors for Non-volatile Memory Applications | 作者: | Gupta M VITA PI-HO HU |
公開日期: | 2022 | 來源出版物: | 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022 | 摘要: | This work investigates the memory window (MW) and current ratio (CR) sensitivities of ferroelectric (Fe) junctionless (JL) transistors, considering the ±10% variation in channel doping (Nc) and film thickness (Tsi), for non-volatile memory applications. While the MW of the Fe JL transistor remains the same, the sensitivity of CR is significant towards the change in Tsi and Nc. The primary reason for the higher CR sensitivity is the heavily doped channel of JL devices and the location of the conduction channel in the bulk of the film. A systematic methodology is highlighted to lower the CR sensitivity while simultaneously improving the MW. Results reported for the first time showcases the design considerations of Fe JL transistors for non-volatile memory applications. © 2022 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85130508782&doi=10.1109%2fVLSI-TSA54299.2022.9771039&partnerID=40&md5=18e3276317b4dd8cf9f6cb0ed69ec455 https://scholars.lib.ntu.edu.tw/handle/123456789/632293 |
DOI: | 10.1109/VLSI-TSA54299.2022.9771039 | SDG/關鍵字: | Nonvolatile storage; Semiconductor doping; Sensitivity analysis; Transistors; Channel dopings; Current ratios; Doped channels; Film-thickness; Heavily doped; High currents; In-channels; Junctionless devices; Junctionless transistors; Memory window; Ferroelectricity |
顯示於: | 電機工程學系 |
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