https://scholars.lib.ntu.edu.tw/handle/123456789/632324
標題: | An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter | 作者: | Lai Y.-P Chang H.-H TAI-CHENG LEE |
關鍵字: | asynchronous; delta-sigma modulator; high resolution; Incremental delta-sigma data converter; low power; zero-crossing-based circuits | 公開日期: | 2022 | 來源出版物: | 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings | 摘要: | A 20 Hz 2nd-order discrete-time incremental sigma-delta modulator with 1-bit quantizer is proposed by utilizing zero-crossing-based integrator with asynchronous clock system. This prototype fabricated in a UMC 28 nm HPC Plus CMOS technology, achieving 11.5-bit ENOB at 40 S/s conversion rate with an over-sampling ratio (OSR) of 256, and yielded a Schreier FoM of 165.5 dB. The modulator occupies an active area smaller than 0.105 mm2 and consumes 141.1 nW. © 2022 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85130468030&doi=10.1109%2fVLSI-DAT54769.2022.9768072&partnerID=40&md5=4c7729d7787cb28fc2147f0bb7bbb7cc https://scholars.lib.ntu.edu.tw/handle/123456789/632324 |
DOI: | 10.1109/VLSI-DAT54769.2022.9768072 | SDG/關鍵字: | Delta sigma modulation; Low power electronics; Modulators; Asynchronoi; Data converter; Delta-sigma; Delta-sigma converters; Discrete time; High resolution; Incremental delta-sigma data converter; Low Power; Zero-crossing-based circuit; Zero-crossings; Timing circuits |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。