https://scholars.lib.ntu.edu.tw/handle/123456789/632488
標題: | A miniature V-band 3-stage cascode LNA in 0.13μm CMOS | 作者: | Lo C.-M Lin C.-S HUEI WANG |
公開日期: | 2006 | 來源出版物: | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 摘要: | A miniature V-Band (50 to 75GHz) 3-stage cascode CMOS LNA implemented in 0.13μm bulk CMOS technology exhibits better than 20dB measured gain from 51 to 57.5GHz in 0.46mm2 die size. The minimum NF is 7.1dB at 56.8GHz. The P1dB is -22dBm, the IIP3 is -12dBm, and the total current is 33mA. © 2006 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-34548823330&partnerID=40&md5=5154734ec46031f851738ba62f61b66e https://scholars.lib.ntu.edu.tw/handle/123456789/632488 |
ISSN: | 1936530 | SDG/關鍵字: | CMOS integrated circuits; Electric current measurement; Gain measurement; Cascode CMOS LNA; Die size; Low noise amplifiers |
顯示於: | 電機工程學系 |
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