First Demonstration of Monolithic 3D Self-aligned GeSi Channel and Common Gate Complementary FETs by CVD Epitaxy Using Multiple P/N Junction Isolation
Journal
Technical Digest - International Electron Devices Meeting, IEDM
Journal Volume
2022-December
ISBN
9781665489591
Date Issued
2022-01-01
Author(s)
Tu, Chien Te
Liu, Yi Chun
Huang, Bo Wei
Chen, Yu Rui
Hsieh, Wan Hsuan
Tsai, Chung En
Chueh, Shee Jier
Cheng, Chun Yi
Ma, Yichen
Abstract
Monolithic 3D self-aligned vertically stacked Ge0.75 Si0.25 nanosheet complementary FETs with multiple P/N junction isolation by in-situ doped CVD epitaxy are experimentally demonstrated. The triple P/N junctions using Ge:B/Ge:P multilayers suppress the leakage current without extra dielectric layers. Both the top pFETs and bottom nFETs have the same uniform GeSi nanosheets thanks to the co-optimization of CVD epitaxy and highly selective HNO3 wet etching (selectivity140). Self-aligned GeSi channels and common gate architecture are fabricated as a CMOS inverter with good voltage transfer characteristics. The post-metallization annealing with the low thermal budget of 400°C improves the inverter characteristics such as switching threshold voltage and voltage gain. The self-aligned 3D stacked GeSi nanosheet pFETs on GeSi nanosheet nFETs without wafer bonding, dielectric isolation, and selective epi regrowth can simplify the process for 3D transistor stacking.
Type
conference paper