A 0.0072-mm210-bit 100-MS/s Calibration-free SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS
Journal
2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
ISBN
9798350334166
Date Issued
2023-01-01
Author(s)
Tsai, Yao Hung
Abstract
A 10-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented by using the digital place-and-route (DPR) tools. The floorplan and blockage constraint for the bootstrapped switch and the comparator are presented to improve the parasitic capacitances caused by the DPR tools, respectively. The redundancy in the capacitive digital-to-analog converter (CDAC) and the on-chip reference buffer are presented to relieve the CDAC settling error. This calibration-free SAR ADC is fabricated in 40-nm CMOS technology and its active area is 0.0072 mm2. To compare with the full-custom method, the DPR flow has speeded up by a factor of 76 to complete the interconnection wires. Its power dissipation is 418-μ W at 100-MS/s and the calculated Walden FoM is 10.9-fJ/c. step at Nyquist frequency.
Subjects
Analog-to-digital converter (ADC) | bootstrapped switch | digital place-and-route (DPR) | double-tail comparator | successive approximation register (SAR)
Type
conference paper