https://scholars.lib.ntu.edu.tw/handle/123456789/634882
標題: | Improved Scalability of Negative Capacitance Junctionless Transistors With Underlap Design | 作者: | Gupta, Manish VITA PI-HO HU |
關鍵字: | Double gate | inversion mode (IM) | junctionless (JL) | negative capacitance (NC) | 公開日期: | 1-八月-2023 | 卷: | 70 | 期: | 8 | 來源出版物: | IEEE Transactions on Electron Devices | 摘要: | Through physical insights and well-calibrated simulations, this work reports on the scalability comparison of negative capacitance (NC) junctionless (JL) and inversion mode (IM) transistors for the technology node (TN) down to 1.5 nm. Due to different operating mechanisms, the distinction in NC effect in JL and IM devices is investigated. Results showcased that NCJL transistors with an optimal underlap (6 nm) outperform NCIM devices as ∼ 2.5× 102 times lower OFF-current ( IOFF) along with higher ON-current (ION) is achieved in NCJL device at a 1.5-nm node. This work provides new opportunities and comprehensively highlights the potential benefits of underlap design in reducing IOFF without compromising ION in NCJL devices at scaled TNs. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/634882 | ISSN: | 00189383 | DOI: | 10.1109/TED.2023.3285511 |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。