Improved Scalability of Negative Capacitance Junctionless Transistors With Underlap Design
Journal
IEEE Transactions on Electron Devices
Journal Volume
70
Journal Issue
8
Date Issued
2023-08-01
Author(s)
Gupta, Manish
Abstract
Through physical insights and well-calibrated simulations, this work reports on the scalability comparison of negative capacitance (NC) junctionless (JL) and inversion mode (IM) transistors for the technology node (TN) down to 1.5 nm. Due to different operating mechanisms, the distinction in NC effect in JL and IM devices is investigated. Results showcased that NCJL transistors with an optimal underlap (6 nm) outperform NCIM devices as ∼ 2.5× 102 times lower OFF-current ( IOFF) along with higher ON-current (ION) is achieved in NCJL device at a 1.5-nm node. This work provides new opportunities and comprehensively highlights the potential benefits of underlap design in reducing IOFF without compromising ION in NCJL devices at scaled TNs.
Subjects
Double gate | inversion mode (IM) | junctionless (JL) | negative capacitance (NC)
Type
journal article