A Sub-Baud-Rate Wireline Receiver With One-Tap DFE
Journal
IEEE Journal of Solid-State Circuits
Start Page
1
End Page
11
ISSN
0018-9200
1558-173X
Date Issued
2024
Author(s)
Yu-Hong Yang
Abstract
A 30-Gb/s sub-baud-rate (SBR) wireline receiver consists of a continuous-time-linear equalizer, a one-tap decision-feedback equalizer, and a clock and data recovery (CDR) circuit using only differential 7.5-GHz quarter-rate clocks. A current-integrating summer with an extra-data-canceling (EDC) technique allows the receiver to operate at a two-phase quarter-rate clocking and achieve low power in the clock distribution. The proposed receiver fabricated in a 28-nm CMOS technology occupies 0.1 mm $^{2}$ and consumes 18 mW.
SDGs
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article