Vertical Interconnections by Electroless Pd Atoms on Immersion Au Surface for Heterogeneous Integration
Journal
Journal of The Electrochemical Society
Journal Volume
171
Journal Issue
7
Start Page
072502
ISSN
0013-4651
1945-7111
Date Issued
2024-07-01
Author(s)
Po-Shao Shih
Jeng-Hau Huang
Simon Johannes Gräfner
Chin-Li Kao
Yung-Sheng Lin
Yun-Ching Hung
DOI
10.1149/1945-7111/ad5c07
Abstract
Electroless Pd atoms were employed to bond vertical interconnection for chip-stacking applications without pressure and at a temperature below 100 °C. Vertical interconnections were created by channeling an electroless Pd plating solution through microchannels, enabling the reduced Pd atoms to assemble naturally within the gaps between two opposing Cu pillars. Notably, the Pd deposition resulted in epitaxial growth along the orientation of the Cu pillar surface, suggesting improved electrical properties for future high-frequency applications. In this study, highly uniform electroless Pd-bonded Cu pillar joints were fabricated using a patterned microfluidic system. The required bonding time was significantly correlated with the plating temperature. Furthermore, the electroless Pd-bonded joints exhibit a robust strength of approximately 55 MPa. Pd exhibits greater skin depth than other plating materials, which helps reduce signal loss and latency during high-frequency signal transmission. This innovative approach offers promise as a potential candidate for future 5G applications requiring low bonding stress and minimal thermal budget.
Subjects
3D integration
electroless plating
low-temperature bonding
microfluidic system
pressure free bonding
Publisher
The Electrochemical Society
Type
journal article