Design and Implementation of a 6.5-Gb/s Multiradix Simplified Viterbi-Sphere Decoder for Trellis-Coded Generalized Spatial Modulation With Spatial Multiplexing
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
30
Journal Issue
12
Start Page
1853
End Page
1866
ISSN
10638210
Date Issued
2022
Author(s)
Wang, Zhe-Yu
Abstract
A simplified Viterbi-sphere decoder (VSD) for trellis-coded generalized spatial modulation (GSM) with spatial multiplexing (TCGSMX) is designed and implemented to exploit the soft information for achieving better performance. Multiple code rates are supported to combat different levels of spatial correlations in fading channels and to offer options for various transmission efficiencies. Hence, the proposed multiradix simplified VSD is configurable to process four radix-2 stages for 1/2 code rate, two radix-4 stages for 2/3 code rate, and one radix-8 stage for 3/4 code rate in one clock cycle to upgrade the throughput by fully pipelined architecture. To reduce the complexity, several techniques are employed, including the efficient settings of survival nodes of sphere decoding and sequence length for backtracing by Viterbi decoding. The chip has been fabricated in TSMC 40-nm CMOS technology. Compared to related works, the implementation provides higher throughput up to 6.5 Gb/s at 1.1-V supply voltage as well as 180.8-MHz operating frequency and consumes 374.3 mW for TCGSMX systems using 16-QAM and code rate of 1/2. © 2022 IEEE.
Subjects
Spatial modulation (SM)
very high speed integrated circuits
Viterbi algorithm
SDGs
Publisher
Institute of Electrical and Electronics Engineers Inc.
Type
journal article