Implementation of a Two-Dimensional FFT/IFFT Processor for Real-Time High-Resolution Synthetic Aperture Radar Imaging
Journal
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Date Issued
2021
Author(s)
Abstract
The demand of high-resolution synthetic aperture radar (SAR) images entails large-size fast Fourier transform (FFT) in the range and azimuth directions and makes real-time processing a challenging task. A 2D-FFT/IFFT processor is implemented to support 8192-, 16384-, and 32768-point range FFT/IFFT and 8192-point azimuth FFT/IFFT. To exploit the burst read/write of external DDR memory for access efficiency, azimuth decomposition is adopted. Besides, normal-order input for azimuth FFT and bit-reversed order input for azimuth IFFT are designed to save latency and storage for re-ordering. The control logic for look-up tables of twiddle factors in normal-order FFT and bit-reversed-order IFFT given azimuth decomposition is derived and a significant ROM-table reduction is achieved. The radix-23 single-path delay feedback (SDF) architecture is employed to reduce the number of complex multipliers and to allow for streaming input/output. A customized floating-point data-path is utilized. The maximum operating frequency is 111MHz of our 2D-FFT/IFFT processor realized by Xilinx ultrascale VU37P HBM FPGA. The SQNR achieves more than 48dB for one transformation and about 38dB for successive 2D- FFT and 2D-IFFT operations. We demonstrate a promising solution of2D FFT/IFFT for real-time SARimaging. © 2021 IEEE.
Event(s)
2021 IEEE Workshop on Signal Processing Systems, SiPS 2021
Subjects
FPGA
Range Doppler algorithm
Synthetic aperture radar
Two-dimensional FFT/IFFT
SDGs
Description
Coimbra, 19 October 2021 through 21 October 2021
Type
conference paper