Interface tailoring for CMOS, cryogenic electronics, and beyond
Journal
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)
Journal Volume
55
Start Page
189083
ISBN (of the container)
979-835033416-6
Date Issued
2023-04-17
Author(s)
H. W. Wan
Y. T. Cheng
L. B. Young
C. K. Cheng
W. S. Chen
Y. H. G. Lin
C. H. Hsu
T. W. Pi
Y. H. Lin
J. Kwo
Abstract
We have tailored high-κ /epi-Si/Ge and /InGaAs interfaces, whose electronic structures were elucidated based on our understanding of the surface electronic structures of Ge, SiGe, epi-Si/Ge, (In)GaAs. Low interface trap densities (Dit's) of (2-4)× 1011eV-1cm-2 and small charge trapping with a high acceleration factor γ=11 were achieved simultaneously in the Ge MOS. We have achieved record low subthreshold slopes (SS) of 22 mV/dec at 77K and Dit's in the high-κ /(In)GaAs planar InGaAs MOSFETs. Superconducting Al films epitaxially grown on sapphire have shown > 1M internal quality factor in the resonators.
Publisher
IEEE
Type
conference paper