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  4. Gallager B LDPC Decoder with Transient and Permanent Errors
 
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Gallager B LDPC Decoder with Transient and Permanent Errors

Journal
IEEE Transactions on Communications
Journal Volume
62
Journal Issue
1
Start Page
15
End Page
28
ISSN
0090-6778
Date Issued
2014-01
Author(s)
Chu-Hsiang Huang  
Yao Li
Lara Dolecek
DOI
10.1109/tcomm.2013.111913.130178
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/722354
Abstract
This paper studies the performance of a noisy Gallager B decoder for regular LDPC codes. We assume that the noisy decoder is subject to both transient processor errors and permanent memory errors. We permit different error rates at different functional components. In addition, for the sake of generality, we allow asymmetry in the permanent error rates of component outputs, and thus we model error propagation in the decoder via a suitable asymmetric channel. We then develop a density evolution-type analysis on this asymmetric channel. The recursive expression for the bit error probability is derived as a function of the code parameters (node degrees), codeword weight, transmission error rate, and the error rates of the permanent and the transient errors. Based on this analysis, we then derive the residual error of the Gallager B decoder for the regime where the transmission error rate and the processing error rates are small. In this regime, we further observe that the residual error rate can be well approximated by a suitable combination of the transient error rate and the permanent error rate at variable nodes, provided that the check node degree is large enough. Based on this insight, we then propose and analyze a scheme for detecting permanent errors and correcting detected residual errors. The scheme exploits the parity check equations of the code and reuses the existing hardware to locate permanent errors in memory blocks. Performance analysis and simulation results show that, with high probability, the detection scheme discovers correct locations of permanent memory errors, while, with low probability, it mislabels the functional memory as being defective. The proposed error detection-and-correction scheme can be implemented in-circuit and is useful in combating failures arising from aging.
SDGs

[SDGs]SDG16

Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article

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