FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
22
Journal Issue
5
Start Page
1150
End Page
1163
ISSN
1063-8210
1557-9999
Date Issued
2014-05
Author(s)
Niraj K. Jha
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article