A Calibration-Free 9.3-ENOB 1-GS/s Pipelined ADC With PVT-Insensitive Nested Ring Amplifiers
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Start Page
1
End Page
1
ISSN
1549-7747
1558-3791
Date Issued
2024
Author(s)
Chao-Yen Hsu
Abstract
This brief presents a nested ring amplifier with dynamic-cascode-bias and gain-boosting techniques. The proposed amplifier achieves a gain of 90 dB while preserving the high-slew capability. The amplifier is employed in a MDAC for a calibration-free 11-bit 1-GS/s single-channel pipelined ADC. Furthermore, the proposed biasing circuits are utilized to alleviate PVT sensitivity. Fabricated in a 28-nm CMOS technology, the ADC achieves a 61.72-dB SFDR and 53.52-dB SNDR at a Nyquist input, while consuming 14.7 mW from a 1-V supply and yielding Schreier and Walden figure-of-merit (FoM) values of 159 dB and 37.9 fJ/conv.-step, respectively.
SDGs
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article