Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards
Part Of
Proceedings - Design Automation Conference
Start Page
1
End Page
2
ISBN (of the container)
979-840070601-1
Date Issued
2024-06-23
Author(s)
Abstract
This paper proposes a power rail routing flow for advanced multi-layered printed circuit boards (PCBs) to optimize segment area and via usage while satisfying IR drop requirements. With increasing current/voltage demands in modern PCBs, ultra-wide power rails may consume most routing space and cause significant routing problems. We present an effective overlap-aware rail sizing technique to distribute routing spaces appropriately according to current/voltage demands and a resistance-aware A*-search algorithm to resolve overlapping regions by rail detouring. Experimental results show that our work significantly outperforms the state-of-the-art rail router in the metal area and runtime, achieving respective reductions of 49% and 28%, without any current/voltage violations.
Event(s)
61st ACM/IEEE Design Automation Conference, DAC 2024
SDGs
Publisher
ACM
Type
conference paper