Conflict-Free and Area-Efficient 4N4P CFET 8T SRAM with Double-Sided Signal Routing for Multibit Compute-in-Memory in AI Edge Devices
Part Of
Technical Digest - International Electron Devices Meeting, IEDM
Start Page
1
End Page
4
ISBN (of the container)
979-835036542-9
Date Issued
2024-12-07
Author(s)
Abstract
As NIP FETs in CFET structures approach optimal driving capabilities, logic performance is enhanced through balanced NIP FET strengths. However, balanced NIP FETs exacerbate readlwrite conflicts in CFET 6T SRAM, resulting in a tighter threshold voltage design window, which complicates effective integration across the chip. This study proposes a conflict-free 4N4P CFET 8T SRAM with double-sided signal routing, avoiding tall vias and redundant transistors while maintaining the same cell area as CFET 6T SRAM. The 4N4P CFET 8T SRAM with balanced NIP FETs demonstrates an 80% larger RSNM, 41 % shorter read time, 11 % shorter write time, 25% lower read power, 14% lower write power, 1.88x faster logic speed at iso-power, and 0.38x lower logic power at iso-speed. Additionally, with improved energy efficiency, the 4N4P CFET 8T SRAM macro supports simultaneous multibit multiply-and-accumulate (MAC) computations for data-centric AI edge device applications.
Event(s)
2024 IEEE International Electron Devices Meeting, IEDM 2024
Publisher
IEEE
Type
conference paper