A Memory-Based Continuous-Flow FFT Processor with a Conflict-Free In-Place Addressing Scheme Supporting Composite Power Points
Journal
2025 IEEE International Symposium on Circuits and Systems (ISCAS)
Series/Report No.
Proceedings IEEE International Symposium on Circuits and Systems
Part Of
Proceedings - IEEE International Symposium on Circuits and Systems
Start Page
1
End Page
5
ISSN
02714310
ISBN (of the container)
979-835035683-0
Date Issued
2025-05-25
Author(s)
Abstract
A configurable fast Fourier transform (FFT) processor capable of computing composite power points becomes prevailing in recent communication and signal processing systems. In this paper, a continuous-flow memory-based FFT processor is designed to support 63 modes from 32 to 4096 points. A conflict-free and in-place addressing scheme is proposed to minimize the number of memory banks and total memory sizes for input buffering, intermediate storage, and output re-ordering. The processing element handles radix-3, radix-4, radix-5, radix-(4•2), radix- 32, radix-42 butterflies using a multi-path delay commutator (MDC) architecture with up to five parallel paths. Besides, the 3-tuple multi-radix representation is adopted for the virtual address generation and thus we can extend the concept of conventional conflict-free and in-place addressing for physical address and bank assignments beyond power-of-2 cases. From the comparison results, our proposed FFT processor architecture demonstrates strong computational efficiency by considering both the arithmetic complexity of butterfly operations and twiddle-factor multipliers as well as throughput.
Event(s)
2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Subjects
Conflict-free addressing
in place
memory-based FFT
mixed-radix
Publisher
IEEE
Description
Conference date:25 May 2025 - 28 May 2025
Type
conference paper