Multi-core Vmin and Worst-core Vmin Prediction using SOMAC
Journal
2025 IEEE 43rd VLSI Test Symposium (VTS)
Start Page
1-7
Date Issued
2025-04-28
Author(s)
Abstract
We propose a complete flow of multi-core minimum operating voltage (Vmin) prediction method using a nondestructive stress test. We process stress-test fail-logs and generate features to predict Vmin. In addition, we select important features by Pearson correlation and F-regression. Then, select specified test patterns that correlate to each core’s Vmin by genetic algorithms to reduce stress test time. Experimental results on advanced 4nm multi-core CPU designs show that the best average RMSE of our predicted Vmin can be as low as 8.30 mV. Also, we have achieved over 66% test pattern reduction rate.
Publisher
IEEE
Type
conference proceedings