Monolithic 3D Macro Integrating CMOS with Ambipolar SONOS Tunnel FET for High Performance Edge-AI Computing Applications
Journal
2025 IEEE International Memory Workshop (IMW)
Start Page
1-4
Date Issued
2025-05-18
Author(s)
Tseng, P. H.
Lee, F. M.
Yang, C. C.
Chiang, H. W.
Huang, C. T.
Lin, Y. H.
Lin, Yu-Yu
Lin, N. C.
Sung, P. J.
Wu, C. T.
Wu, W. F.
Shen, C. H.
Hou, T. H.
Cheng, H. Y.
Yeh, T. H.
Lee, M. H.
Hsieh, K. Y.
Abstract
We developed a monolithic 3D (M3D) macro with CMOS and ambipolar SONOS tunnel FET (TFET) for edge-AI computing applications. The substrate-level (Tier-1) CMOS transistors for logic operations have good thermal stability to withstand the low-temperature TFETs fabrication process (6V) for multi-level data storage (> 10 levels). Among the potential applications is the in-memory range search for the memory augmented neural network (MANN). The data range can be pre-defined by different TFET device lengths and/or by varying the drain bias. The novel range computing macro enhances data matching capability between the query and objects using the K-nearest neighbor (KNN) algorithm. Simulation experiments with the CUB-200 dataset showed high voting accuracy up to 86.5% (Cosine similarity baseline: 87.7%) in few-shot learning (FSL) scenarios. The effects from TFET subthreshold swing, matching range, and input dimensions on the MANN accuracy optimization are discussed.
Publisher
IEEE
Type
conference proceedings