First Demonstration of Monolithic 3-Tier Nanosheet Transistor Stacking with Split Gate Featuring Tri-State Inverter/Half Sram Functionalities
Journal
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Start Page
1-3
Date Issued
2025-06-08
Author(s)
Huang, Bo-Wei
Liu, Ying-Qi
Yao, Ching-Wang
Chen, Wei-Jen
Lin, Min-Kuan
Lin, Xin-Yuan
Cheng, Chun-Yi
Huang, Yi
Lin, Ding-Wei
Lu, Chih-Hsuan
Tsai, Tsung-Han
Abstract
Monolithic three-tier transistor stackings with GeSi nanosheets, split gate, and multiple pn layer isolation are demonstrated for the first time. The split-gate process enables one common-gate CFET and one nFET underneath to achieve 6T STAM design with 3T footprint. The functionalities of tristate inverters and half-SRAM (1PD/1PU/1PG) of monolithic three-tier transistor stacking are successfully demonstrated.
SDGs
Publisher
IEEE
Type
conference paper