Optimizing CFET Parasitic Capacitance and Performance Through Middle Dielectric Isolation and Middle via Integration
Journal
2025 Silicon Nanoelectronics Workshop (SNW)
Start Page
6-7
Date Issued
2025-06-08
Author(s)
Abstract
This work presents a comprehensive study on the impact of Middle Dielectric Isolation (MDI) layer count on parasitic capacitance and performance in CFET ring oscillator (RO) circuits. Using calibrated 3D CFET structures at 1 nm node, we evaluate configurations with 2, 3, and 4 MDI layers. Results show that each reduction in MDI layer count improves RO performance by an average of 6.39%, primarily due to a decrease in parasitic capacitance between input and output nodes. To further optimize performance, a middle via (MV) structure is introduced that significantly reduces the dominant capacitance component by minimizing output metal area. Depending on MV placement, parasitic capacitance is reduced by up to 14%, leading to RO frequency gains of 6.77% for 4 MDI layers. For the 4-layer MDI case, MV integration achieves greater performance improvement than MDI layer count reduction alone. These findings provide key insights for optimizing CFET design by balancing process flexibility and electrical performance.
Publisher
IEEE
Type
conference paper