An All-Digital Distributed Power Management Architecture for Dynamic Voltage and Frequency Scaling (DVFS) for Multi-Core Processor
Journal
IEEE Transactions on Industry Applications
Start Page
1
End Page
12
ISSN
0093-9994
1939-9367
Date Issued
2025-10-17
Author(s)
Abstract
This paper presents an all-digital distributed power management architecture and circuit for multi-core processors in system-on-chip (SoC) applications, achieving dynamic voltage and frequency scaling (DVFS). Conventional architectures have issues such as not being fully on-chip, containing analog circuits and reference voltage, not providing multiple outputs, and not being suitable for multi-core processors. To solve the issues, the proposed master-slave structure provides a compact, simple, and scalable architecture. The DLDO-type power supply topology endows it with high power density and enables full on-chip integration. By integrating the frequency and voltage modulation loops, the system inherently optimizes its operating point. This all-digital control approach is well-suited for integration with the processor's digital circuits and doesn't even need any DC reference voltage. The proposed design provides independent, optimized power supply levels to each computing core, particularly under sub-1V low-voltage conditions, thereby minimizing energy per operation. This work was fabricated in a 28nm CMOS process to verify the proposed circuit.
Subjects
all-digital phase-locked loop (AD-PLL)
Digital low-dropout regulator (DLDO)
Dynamic voltage and frequency scaling (DVFS)
energy efficient
low power
million instructions per second (MIPS)
system-on-chip (SoC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article