Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Journal
Proceedings - International Test Conference
Start Page
196
End Page
205
ISSN
10893539
ISBN (of the container)
979-833157041-5
ISBN
[9798331570415]
Date Issued
2025-09-20
Author(s)
Liu, Min-Hsin
Cheng, Ding-Wei
Nigh, Chris
Goh, Szu Huat
Chern, Mason
Hsieh, Bing-Han
Kundu, Subhadip
Abstract
At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vmin pose a risk of over-testing and production yield loss. This is particularly problematic if the Vmin of the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This paper describes an example case study of Vmin debug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vmin by preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vmin by 28.83mV to 39.33mV with 0% to 0.5% pattern count inflation.
Event(s)
2025 IEEE International Test Conference, ITC 2025
Subjects
Delay Test
Diagnosis
Unconstrained Path
Vmin
SDGs
Publisher
Institute of Electrical and Electronics Engineers Inc.
Type
conference paper