A Double Negative GM-based LC Chaotic Circuit for a Random Number Generator
Journal
International SoC Design Conference 2025, ISOCC 2025 - Proceedings of Technical Papers
Start Page
1-2
ISBN (of the container)
979-833158642-3
Date Issued
2026-01-14
Author(s)
Lee, Wan-Yi
Abstract
An LC chaotic circuit is proposed for a high-speed random number generator (RNG). Combining two cross-coupled pairs to form a negative nonlinear resistance to sustain chaotic characteristics, the proposed circuit achieves a 2.5-GHz chaotic oscillation. Designed in a 28-nm CMOS technology, the LC chaotic generator achieves a 2.5-Gb/s code rate from a 1-V supply with 1.092 mW power consumption.
Event(s)
22nd International SoC Design Conference, ISOCC 2025
Subjects
chaotic
LC oscillation random number generator(RNG)
Publisher
IEEE
Type
conference paper