Wafer-Scale Low-Power 2D CFET Logic Enabled by Single-Crystal Dielectrics: Experimental Demonstration and 1-nm-Node Projection
Journal
Technical Digest - International Electron Devices Meeting, IEDM
Start Page
1
End Page
4
ISSN
01631918
ISBN (of the container)
979-833156785-9
Date Issued
2026-01-30
Author(s)
Yang, Ni
Lu, Yu-Cheng
Zhang, Ji
Wang, Zeheng
Zheng, Fangyuan
Li, Lingqi
Liu, Haomin
Huang, Lin-Yun
Li, Chenyang
Yao, Chengdong
Yang, Pengfei
Li, Wanying
Meng, Wanqing
Yip, Pak San
Ki, Dong-Keun
Ang, Kah-Wee
Liang, Geng-Chiau
Wan, Yi
Li, Sean
Huang, Jing-Kai
Li, Lain-Jong
Abstract
We demonstrate a CFET technology that combines wafer-scale single-crystal TiO2 dielectrics with vertically stacked n-MoS2/p-WSe2 channels. A release-transfer process yields atomically flat TiO2 films with sub-nanometre CET. The resulting CFET inverters switch rail-to-rail across a broad voltage range (Vdd = 0.1 V to 1 V) with record-low standby power, high gain, and robust noise margins, validated by wafer-scale NAND/NOR gates. TCAD extrapolation at the 1nm node indicates that 4N2P six-transistor SRAM arrays on this platform surpass projections based on Si-GAA in terms of speed and energy, underscoring the viability of 2D semiconductors for next-generation logic.
Event(s)
2025 IEEE International Electron Devices Meeting, IEDM 2025
Publisher
IEEE
Type
conference paper