An Energy-Efficient 4th-Order CT Delta-Sigma ADC with Time-Interleaved Analog-CIFF-Assisted Digital-EF NSSAR Quantizer
Journal
2025 IEEE Asian Solid-State Circuits Conference, A-SSCC 2025 - Proceedings
Start Page
118
End Page
120
ISBN (of the container)
979-833158631-7
Date Issued
2026-01-28
Author(s)
Chang, Chih-Kai
Abstract
The rapid growth of Internet-of-Things (IoT) devices drives the demand for ADCs that deliver high resolution and moderate bandwidth with ultra-low power consumption. Continuous-time DeltaSigma Modulators (CT-DSMs) are favored for their inherent antialiasing and power-efficient resistive loads. Hybrid CT-DT architectures employing analog filters like Cascaded-IntegratorFeedforward (CIFF) and Error-Feedback (EF) are widely used to improve noise shaping and power efficiency further. However, aggressive noise shaping typically requires power-hungry active devices. Passive analog filters reduce power but suffer from lossy noise transfer functions, especially in high-order designs. Digital noise coupling (DNC) structures [1] have emerged to realize highorder digital EF filters without extra active analog circuits and offer precise, stable coefficients. However, DNC demands a highresolution residue quantizer to suppress extra quantization noise, limiting achievable sampling speeds. Recent works adopted analog noise coupling to reduce this noise [2] but require calibration due to coefficient variations. This work proposes a 4th-order CT-DSM with a calibration-free 2nd-order noise-shaping SAR quantizer (NS-SAR QTZ). The novel Analog-CIFF-assisted Digital-EF (ACIFF-assisted DEF) technique effectively suppresses residue quantization noise, alleviating speed limitations. A two-channel time-interleaved structure further boosts sampling rate, enabling a high-speed, energy-efficient ADC suitable for next-generation IoT applications.
Event(s)
2025 IEEE Asian Solid-State Circuits Conference, A-SSCC 2025
Publisher
IEEE
Type
conference paper