Prospects and Challenges for Two-Dimensional Transition Metal Dichalcogenide Based Logic Devices
Journal
2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Start Page
1
End Page
2
Date Issued
2026-03-01
Author(s)
Hung, Terry Y.T.
Chang, Shu-Jui
Chung, Yun-Yan
Chou, Ang-Sheng
Yun, Wei-Sheng
Wu, Wen-Chia
Li, Meng-Zhan
Ku, Shuer
Mao, Po-Sen
Chou, Sui-An
Chen, Edward
Su, Sheng-Kai
Heh, Dawei
Lin, Yu-Tung
Chou, Bo-Jhih
Chang, Yu-I
Yang, Chueh-Cheng
Wang, Shin-Yuan
Lin, Kris K.H
He, Liang-Ching
Ho, Yi-Fan
Lin, Kuan-Bo
Liu, Wei-Tung
Yang, Jen-Hao
Huang, Shu-Wei
Lin, Erh-Chen
Lin, Chun-Chun
Liu, Yen-Hui
Hsu, Chen-Feng
Lee, T.Y.
Vellianitis, Georgios
van Dal, Mark
Liu, Bo-Heng
Kei, Chi-Chung
Yang, Ying-Mei
Chen, Tse-Ming
Lin, Chun-Liang
Chang, Wen-Hao
Chien, Chao-Hsin
Hu, Chenming
Li, Ming-Yang
Cheng, Chao-Ching
Woon, Wei-Yen
Radu, Iuliana P.
Cao, Min
Abstract
The high demand for data processing necessitates continued transistor scaling in both area and performance. Two-dimensional (2D) materials, such as transition metal dichalcogenides, offer a promising avenue for aggressive scaling, yet significant breakthroughs are still needed for their technological adoption. While substantial progress has been made in improving channel quality, scaling gate dielectrics, and contact pitch miniaturization to the relevant value, challenges in contact, especially in p-type channel and gate integration remain.In this talk, we will explore the current state-of-the-art for 2D material transistors [1], detailing critical challenges focusing on the high access resistance and gate stack. We highlight the need for p-contact engineering schemes beyond those employed in current back-gated devices. Compatibility with nanosheet/gate-all-around architectures is highly desired [2]. Recent advances in device scaling, gate stack scaling, and the required mechanical strength for nanosheets will be discussed.Contact length scaling and increasing ION with channel length scaling down to at least 12nm with low contact resistance are demonstrated, as well as very scaled device length high performance n-type transistor [3], [4]. Optimizing the interfacial layer and surface treatment leads to the ~1.6x mobility enhancement, achieving relevant mobility at a 1.4nm effective oxide thickness [5]. Mechanical strength, a key parameter in nanosheet integration, especially for 2D materials, is enabled by introducing bilayer MoS2. Meanwhile, contact length up to 30nm can be achieved through C-contact geometry. For contact integration, nearly epitaxial metal deposited by ALD shows a work function of ~6.0 eV with WSe2, making it suitable for PMOS. Combined with Phosphorous doping, all elements for fab-compatible contact module are included.We will aim to provide a summary guide of high-value research topics for 2D materials in very scaled transistors.
Subjects
logic devices
transition metal dichalcogenide
Two dimensional materials
Publisher
IEEE
Type
conference proceedings