公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2010 | QoS aware BiNoC architecture | Lo, S.-H.; Lan, Y.-C.; Yeh, H.-H.; Tsai, W.-C.; Hu, Y.-H.; SAO-JIE CHEN | 2010 IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010 | | | |
2011 | Rate-allocation for spatially scalable video coding | Peng, G.-J.; Hwang, W.-L.; SAO-JIE CHEN | ISPA 2011 - 7th International Symposium on Image and Signal Processing and Analysis | | | |
2005 | Real-time implementation of noise-immune gradient-based edge detection | Hsiao, P.-Y.; Wen, H.; Chen, Y.-P.; SAO-JIE CHEN | ISSCS 2005: International Symposium on Signals, Circuits and Systems | | | |
2006 | Real-time realisation of noise-immune gradient-based edge detector | Hsiao, P.-Y.; Chen, C.-H.; Wen, H.; SAO-JIE CHEN | IEE Proceedings: Computers and Digital Techniques | 13 | 7 | |
2012 | Reconfigurable networks-on-chip | Chen, S.-J.; Lan, Y.-C.; Tsai, W.-C.; Hu, Y.-H.; SAO-JIE CHEN | Reconfigurable Networks-on-Chip | | | |
1994 | Reflexive Object-Oriented Software Engineering | Hsu, F. M.; See, W. B.; Fuh, R. M.; 陳少傑 ; Chen, Sao-Jie | Fourth Workshop on Object-Oriented Technology | | | |
2023 | A Robust Super-Regenerative Receiver with Optimal Detection on BER Level | Su, Yi Pei; Huang, Chao Yen; SAO-JIE CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | 0 | 0 | |
1991 | Routing Area Compaction Based On Iterative Construction | Tsai, C.-C.; Chen, S.-J.; Hsiao, P.-Y.; Feng, W.-S.; SAO-JIE CHEN | Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an | | | |
1994 | A Routing System for the PGA Package | Wang, C. M.; Tsai, C. C.; 陳少傑 ; Chen, Sao-Jie | 5th VLSI Design/CAD Symposium | | | |
1990 | Routing Techniques in Staircase Channels | Fang, S. C.; 陳少傑 ; 馮武雄; Chen, Sao-Jie ; Feng, Wu-Shiung | 1990 2nd Workshop on CAD for VLSI | | | |
1994 | Row-Based and Symmetrical Field Programmable Gate Arrays Routing | Chen, J. Y.; 陳少傑 ; Ho, J. M.; Chen, Sao-Jie | 5th VLSI Design/CAD Symposium | | | |
1994 | Scheduling algorithm for nonpreemptive multiprocessor tasks | Lin, J.-F.; SAO-JIE CHEN | Computers and Mathematics with Applications | 13 | 10 | |
1994 | Scheduling parallel tasks on hypercubes | Lin, J.-F.; SAO-JIE CHEN | Electronics Letters | 0 | 0 | |
1994 | Scheduling Parallel Tasks With Setup Time on Hypercube Systems | Lin, J. F.; See, W. B.; 陳少傑 ; Chen, Sao-Jie | International Computer Symposium | | | |
2009 | Simdcode generation for multimedia applications | Lin, G.-H.; Wen, Y.-N.; Wu, X.-L.; Chen, S.-J.; Su, A.P.; SAO-JIE CHEN | International Journal of Electrical Engineering | | | |
2003 | Simultaneous routing and buffering in floorplan design | Fang, J.P.; Tong, Y.-S.; SAO-JIE CHEN | International Symposium on VLSI Technology, Systems, and Applications | 1 | 0 | |
2004 | Simultaneous routing and buffering in SOC floorplan design | Fang, J.P.; Tong, Y.-S.; SAO-JIE CHEN | IEE Proceedings: Computers and Digital Techniques | 5 | 5 | |
2004 | Software platform for embedded software development | See, W.-B.; Hsiung, P.-A.; Lee, T.-Y.; SAO-JIE CHEN | Lecture Notes in Computer Science | | | |
1996 | A stable partitioning algorithm for VLSI circuits | Cherng, Jong-Sheng; Chen, Sao-Jie | Custom Integrated Circuits Conference, 1996. | 0 | 0 | |
1996 | Stable partitioning algorithm for VLSI circuits | Cherng, Jong-Sheng; SAO-JIE CHEN | Custom Integrated Circuits Conference | | | |