公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2003 | Simultaneous routing and buffering in floorplan design | Fang, J.P.; Tong, Y.-S.; SAO-JIE CHEN | International Symposium on VLSI Technology, Systems, and Applications | 1 | 0 | |
2004 | Simultaneous routing and buffering in SOC floorplan design | Fang, J.P.; Tong, Y.-S.; SAO-JIE CHEN | IEE Proceedings: Computers and Digital Techniques | 5 | 5 | |
2003 | Tile-based power planning during floorplanning | Fang, J.P.; SAO-JIE CHEN | IEEE International SOC Conference, SOCC 2003 | 0 | 0 |