公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2007 | Modeling and automatic failure analysis of safety-critical systems using extended safecharts | Chen, Y.-R.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN | Lecture Notes in Computer Science | | | |
2016 | Modeling and Simulation of Quantum-Well Infrared Photodetectors | S. J. Chen; H. P. Yang; D. J. Lin; G. Liu; SAO-JIE CHEN | IEEE International System-on-Chip Conference (SOCC) | | | |
2005 | Multilevel full-chip routing for the X-based architecture | Ho, Tsung-Yi; Chang, Chen-Feng; Chang, Yao-Wen ; Chen, Sao-Jie | Design Automation Conference | | | |
2005 | Multilevel full-chip routing for the X-based architecture. | SAO-JIE CHEN ; Chang, Chen-Feng; YAO-WEN CHANG ; Ho T.-Y | Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005 | 39 | 0 | |
2004 | Multilevel routing with antenna avoidance | Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; SAO-JIE CHEN | International Symposium on Physical Design | | | |
2004 | Multilevel routing with antenna avoidance. | Ho, Tsung-Yi; SAO-JIE CHEN ; YAO-WEN CHANG | Proceedings of the International Symposium on Physical Design | 36 | 0 | |
2006 | Multilevel routing with jumper insertion for antenna avoidance | Ho, T.-Y.; YAO-WEN CHANG ; SAO-JIE CHEN | Integration, the VLSI Journal | 5 | 2 | |
2004 | Multilevel routing with jumper insertion for antenna avoidance | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie | IEEE International SOC Conference | 0 | 0 | |
2006 | Multiple-symbol parallel CAVLC decoder for H.264/AVC | Wen, Y.-N.; Wu, G.-L.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS | 27 | 0 | |
2020 | Network-cognitive traffic control: A fluidity-aware on-chip communication | Tsai, W.-C.; SAO-JIE CHEN ; Hu, Y.-H.; Chiang, M.-L. | Electronics (Switzerland) | 2 | 2 | |
2012 | Networks on Chips: Structure and design methodologies | Tsai, W.-C.; Lan, Y.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | Journal of Electrical and Computer Engineering | 60 | 0 | |
2012 | Networks-on-chip: Architectures, design methodologies, and case studies | AN-YEU(ANDY) WU ; SAO-JIE CHEN ; Chen, S.-J.; Wu, A.-Y.A.; Xu, J.; AN-YEU(ANDY) WU ; SAO-JIE CHEN | Journal of Electrical and Computer Engineering | | | |
1991 | New iterative construction approach to routing with compacted area | Tsai, C.-C.; Chen, S.-J.; Hsiao, P.-Y.; Feng, W.-S.; SAO-JIE CHEN | IEE Proceedings E: Computers and Digital Techniques | | | |
1990 | A New Method for Two-Dimensional VLSI Layout Compaction Design | Chen, H. F.; Hsiao, P, Y.; 馮武雄; 陳少傑 ; Feng, Wu-Shiung; Chen, Sao-Jie | 1990 2nd Workshop on CAD for VLSI | | | |
1990 | A New Strategy for Reconfigurable Arrays Using Free-Most Method | Fang, S. C.; 陳少傑 ; Lee, S. L.; Liou, J. C.; Chen, Sao-Jie | 1990 Interntational Elextron Devices and Materials Symposium | | | |
1998 | NEWS: A net-even-wiring system for the routing on a multilayer pga package | Tsai, C.-C.; Wang, C.-M.; Chen, S.-J.; SAO-JIE CHEN | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 25 | 23 | |
2013 | Non-minimal, turn-model based NoC routing | Tsai, W.-C.; Chu, K.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | Microprocessors and Microsystems | 7 | 5 | |
1991 | Novel graph-based algorithms for reconfigurable arrays | Fang, Sung-Chum; Chen, Sao-Jie ; Lee, S.L. | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
2013 | Novel time-multiplexing bidirectional on-chip network | Wei, C.-J.; Weng, Y.-Y.; Tsai, W.-C.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | International System on Chip Conference | 1 | 0 | |
1994 | Object-Oriented Synthesis Application Tool | Hsiung, P. A.; 陳少傑 ; Chen, Sao-Jie | 1994 4th Wrokshop on Object-Oriented Technology | | | |