公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2000 | A sigma-delta modulation based BIST scheme for mixed-signal circuits | JIUN-LANG HUANG ; Cheng, K.-T. | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 27 | 0 | |
2011 | Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs | W.-A. Lin; C.-C. Li; J.-L. Huang; JIUN-LANG HUANG | VLSI Test Symposium | 1 | 0 | |
2008 | Software-Based Self-Testing | Huang, J.-L.; Tim, K.-T.; JIUN-LANG HUANG | System-on-Chip Test Architectures | | | |
2017 | Source code transformation for software-based on-line error detection | T.-Y. Tsai; J.-L. Huang; JIUN-LANG HUANG | IEEE Conference on Dependable and Secure Computing | 3 | 0 | |
1999 | Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. | Huang, Jiun-Lang; Pan, Chen-Yang; Cheng, Kwang-Ting; JIUN-LANG HUANG | 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA | | | |
1999 | Specification back-propagation and its application to fault simulation of analog/mixed-signal circuits | J. L. Huang; C. Y. Pan; K. T. (Tim) Cheng; JIUN-LANG HUANG | VLSI Test Symposium | 12 | | |
2015 | A static bidirectional learning technique to accelerate test pattern generation | J.-H. Pan; K.-W. Yeh; J.-L. Huang; JIUN-LANG HUANG | International SoC Design Conference | 0 | 0 | |
2011 | Structural and optical properties of InGaN/GaN multiple quantum well light emitting diodes grown on (1122) facet GaN/sapphire templates by metalorganic chemical vapor deposition | Huang, J.-L.; Wang, L.S.; Lai, Y.-S.; Lee, Y.-C.; Qiu, Z.R.; Liu, S.; Wuu, D.-S.; Feng, Z.C.; JIUN-LANG HUANG | Proceedings of SPIE - The International Society for Optical Engineering | | | |
2013 | SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN | Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG | | | | |
2013 | Synergistic reliability and yield enhancement techniques for embedded SRAMs | S.-K. Lu; H.-H. Huang; J.-L. Huang; P. Ning; JIUN-LANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 8 | |
2000 | Test point selection for analog fault diagnosis of unpowered circuit boards | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | | | |
2022 | Test Response Compaction for Software-Based Self-Test | Liang, Jia Ruei; Hsieh, Ya Ni; JIUN-LANG HUANG | Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 | 0 | 0 | |
2019 | Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime | Chen, K.-H.; Chen, C.-Y.; JIUN-LANG HUANG | Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 | 3 | 0 | |
2012 | Testing and calibration of SAR ADCs by MCT-based bit weight extraction | Huang, X.-L.; Chen, H.-I.; Huang, J.-L.; Chen, C.-Y.; Kuo-Tsai, T.; Huang, M.-F.; Chou, Y.-F.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | | | |
2000 | Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000 | | | |
2008 | Testing LCD Source Driver IC with Built-On-Scribe-Line Test Circuitry | J.-J. Huang; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 | |
2002 | Testing Second-Order Delta-Sigma Modulators using Pseudo-Random Patterns | C. K. Ong; J. L. Huang; K. T. Cheng; JIUN-LANG HUANG | Microelectronics Journal | 6 | 3 | |
2012 | Time-resolved and temperature-varied photoluminescence studies of InGaN/GaN multiple quantum well structures | Liu, L.; Wang, W.; Huang, J.-L.; Hu, X.; Chen, P.; Huang, J.-J.; Feng, Z.C.; JIUN-LANG HUANG | Proceedings of SPIE - The International Society for Optical Engineering | | | |
2011 | Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains | Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 1 | |
2012 | Welcome message | Wu, C.-W.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | | | |