公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2005 | An On-Chip Random Jitter Testing Technique Using Low Tap-Count Delay Lines | JIUN-LANG HUANG | International Mixed-Signal Testing Workshop | | | |
2001 | An on-chip short-time interval measurement technique for testing high-speed communication links | J.L. Huang; K.T. Cheng; JIUN-LANG HUANG | VLSI Test Symposium | 24 | | |
1997 | Analog fault diagnosis for unpowered circuit boards | JIUN-LANG HUANG ; Cheng, Kwang-Ting | IEEE International Test Conference (TC) | | | |
2009 | Analog-to-Digital Converter | Jiun-Lang Huang; Jui-Jer Huang; Chuan-Che Lee; JIUN-LANG HUANG | | | | |
2021 | Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors | Chen, Kai Hsun; Yang, Bo Yi; Liang, Jia Ruei; Chen, Hung Lin; JIUN-LANG HUANG | Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 | 2 | 0 | |
2010 | A robust ADC code hit counting technique | J.-L. Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang; JIUN-LANG HUANG | Design, Automation & Test in Europe | 1 | | |
2000 | A BIST scheme for on-chip ADC and DAC testing | Huang, J.-L.; Ong, C.-K.; Cheng, K.-T.; JIUN-LANG HUANG | Proceedings -Design, Automation and Test in Europe, DATE | | | |
2011 | Broadcast test pattern generation considering skew-insertion and partial-serial scan | C.-J. Lin; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 3 | 0 | |
2012 | A built-in characterization technique for 1-bit/stage pipelined ADC | Chou, Y.-H.; Huang, J.-L.; Huang, X.-L.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | | | |
2008 | Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signals, Sensors, and Systems Test Workshop | 6 | 0 | |
2009 | Ch. 8 Logic and Circuit Simulation | J.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG | Electronic Design Automation: Synthesis, Verification, and Test | | | |
2007 | Chap. 11 Software-Based Self-Testing | J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | System on Chip Test Architectures | | | |
2006 | Chap. 3: Logic and Fault Simulation | J.-L. Huang; James C.-M. Li; Duncan M. (Hank) Walker; JIUN-LANG HUANG | VLSI Test Principles and Architectures | | | |
2000 | Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-test | Tofte, Jan Arild; Ong, Chee-Kian; JIUN-LANG HUANG ; Cheng, Kwang-Ting | Proceedings of the IEEE VLSI Test Symposium | | | |
2000 | Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. | Tofte, Jan Arild; Ong, Chee-Kian; Huang, Jiun-Lang; Cheng, Kwang-Ting (Tim); JIUN-LANG HUANG | 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada | | | |
2009 | Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automatic Conference | | | |
2009 | A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays. | Lin, Chen-Wei; JIUN-LANG HUANG | JCP | | | |
2011 | Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing | Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG | International Test Conference | 3 | 0 | |
2009 | Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC | X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 1 | 0 | |
2018 | Conference Reports: Report on 2017 IEEE Asian Test Symposium | Li, Jin-Fu; JIUN-LANG HUANG | IEEE Design and Test | 0 | 0 | |