公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2016 | CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator | K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 1 | 1 | |
2010 | CSER: BISER-based concurrent soft-error resilience | CHIEN-MO LI ; JIUN-LANG HUANG ; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; CHIEN-MO LI ; JIUN-LANG HUANG | VLSI Test Symposium (VTS) | | | |
2000 | A delta-sigma modulation based BIST scheme for mixed-signal systems | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000 | | | |
2017 | Design and implementation of an EG-pool based FPGA formatter with temperature compensation | Y.-K. Huang; K.-T. Li; C.-L. Hsiao; C.-A. Lee; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 | |
2018 | Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter | Hou, G.-H.; Huang, W.-C.; Huang, J.-L.; Kuo, T.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | | | |
2015 | Design and Implementation of an FPGA-Based Data/Timing Formatter | Y.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 6 | 6 | |
2008 | Design of a Fault Tolerant Carry Lookahead Adder | C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG | International Test Synthesis Workshop | | | |
2015 | Design, automation, and test for low-power and reliable flexible electronics | T.-C. Huang; JIUN-LANG HUANG ; K.-T. Cheng | Foundations and Trends in Electronic Design Automation | 10 | 0 | |
2009 | Diagnosing integrator leakage of single-bit first-order Δσ modulator using DC input | Huang, X.-L.; Yang, C.-Y.; JIUN-LANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | | | |
2020 | DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator | Yeh, K.-W.; JIUN-LANG HUANG | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | 0 | 0 | |
2006 | Extracting Random Jitter in the Existence of Sinusoidal Jitter | JIUN-LANG HUANG | International Mixed-Signal Testing Workshop | | | |
2013 | Fault Scrambling Techniques for Yield Enhancement of Embedded Memories | S.-K. Lu; H.-C. Jheng; M. Hashizume; J.-L. Huang; P. Ning; JIUN-LANG HUANG | Asian Test Symposium | 5 | 0 | |
2013 | Foreword | Wang, S.-J.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | | | |
2018 | Foreword: 26th IEEE Asian test symposium (ATS 2017) | Huang, J.-L.; Li, J.-F.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | | | |
2011 | FPAA implementation and validation of an SC integrator leakage measurement technique | Du, N.-T.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | | | |
2019 | An FPGA-Based Data Receiver for Digital IC Testing. | Huang, Wei-Chen; Hou, Guan-Hao; Huang, Jiun-Lang; Kuo, Terry; JIUN-LANG HUANG | IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019 | | | |
2014 | FPGA-Based Subset Sum Delay Lines | C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2020 | Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model | Chen, C.-Y.; Cheng, C.-H.; JIUN-LANG HUANG ; Chakrabarty, K. | Proceedings of the European Test Workshop | 3 | 0 | |
2011 | Guest Editors' Introduction: A Promising Alternative to Conventional Silicon | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | Ieee Design & Test of Computers | | 1 | |
2011 | Histogram-based calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCs | Huang, X.-L.; Kang, P.-Y.; Yu, Y.-C.; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications (JETTA) | | | |