https://scholars.lib.ntu.edu.tw/handle/123456789/153561
標題: | 5.7 GHz low-power variable-gain LNA in 0.18 μm CMOS | 作者: | Wang, Y.S. LIANG-HUNG LU |
公開日期: | 一月-2005 | 卷: | 41 | 期: | 2 | 起(迄)頁: | 66-68 | 來源出版物: | Electronics Letters | 摘要: | A variable-gain low-noise amplifier (LNA) suitable for low-voltage and low-power operation is designed and implemented in a standard 0.18 μm CMOS technology. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7 GHz LNA exhibits 16.4 dB gain, 3.5 dB noise figure and 8 dB gain tuning range with good input and output return losses. The LNA consumes 3.2 mW DC power from a supply voltage of 1 V A gain/power quotient of 5.12 dB/mW is achieved in this work. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/200704191001030 https://www.scopus.com/inward/record.uri?eid=2-s2.0-13844255496&doi=10.1049%2fel%3a20057230&partnerID=40&md5=90a03e91418283fd2743a97f40d305db |
ISSN: | 00135194 | 其他識別: | 0013-5194 | DOI: | 10.1049/el:20057230 | SDG/關鍵字: | CMOS integrated circuits; Electric impedance; Energy dissipation; Energy utilization; Gain control; MOSFET devices; Resonance; Signal processing; Spurious signal noise; Topology; Tuning; Low-noise amplifier (LNA); Low-power operation; Power quotient; Small-signal gain; Amplifiers (electronic) |
顯示於: | 電機工程學系 |
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