https://scholars.lib.ntu.edu.tw/handle/123456789/173538
Title: | 用於低電壓高速超大型積電之100 奈米絕緣體上矽具LDD 之
金氧半SPICE 元件模型(1/3) A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI nMOS Devices Considering Fringing Electric Field Effects |
Authors: | 郭正邦 | Issue Date: | 31-Jul-2004 | Publisher: | 臺北市:國立臺灣大學電子工程學研究所 | URI: | http://ntur.lib.ntu.edu.tw//handle/246246/20015 | Other Identifiers: | 922218E002029 | Rights: | 國立臺灣大學電子工程學研究所 |
Appears in Collections: | 電子工程學研究所 |
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922218E002029.pdf | 756.47 kB | Adobe PDF | View/Open |
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