https://scholars.lib.ntu.edu.tw/handle/123456789/303244
標題: | Minimizing inter-clock coupling jitter | 作者: | Hsiao, M.-F. Marek-Sadowska, M. SAO-JIE CHEN |
關鍵字: | Capacitance; Clocks; Coupling circuits; Crosstalk; Frequency; Jitter; Routing; Signal synthesis; Topology; Wires | 公開日期: | 2003 | 卷: | 2003-January | 起(迄)頁: | 333-338 | 來源出版物: | International Symposium on Quality Electronic Design, ISQED | 摘要: | Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. Besides, in modern chip designs, there is usually more than one clock net, and some-times even tens of them. It is therefore imperative to design clock topologies to prevent possible crosstalk among them. In this paper, we address the inter-clock crosstalk. We propose algorithms to design clock topology and to perform routing minimizing the effective crosstalk. Our experimental results show a significant reduction of clock jitter compared to the conventional clock tree synthesis which does not take into account the inter-clock crosstalk effects. © 2003 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-48349121765&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/303244 |
ISSN: | 19483287 | DOI: | 10.1109/ISQED.2003.1194754 | SDG/關鍵字: | Capacitance; Coupled circuits; Crosstalk; Design; Jitter; Timing jitter; Topology; Wire; Chip performance; Clock tree synthesis; Crosstalk effect; Crosstalk noise; Deep sub-micron technology; Frequency; Routing; Signal synthesis; Clocks |
顯示於: | 電機工程學系 |
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