https://scholars.lib.ntu.edu.tw/handle/123456789/333734
Title: | A jitter-tolerance-enhanced CDR using a GDCO-based phase detector | Authors: | Che-Fu Liang Sy-Chyuan Hwu SHEN-IUAN LIU |
Issue Date: | Jun-2007 | Start page/Pages: | 274-275 | Source: | 2007 Symposium on VLSI Circuits | Abstract: | A jitter-tolerance-enhanced 10Gb/s clock/data recovery (CDR) is presented. By using a gated-digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector achieves a wide linear range and its jitter tolerance is enhanced without sacrificing the jitter transfer. It has been fabricated in 0.13um CMOS technology and consumes 60mW from a 1.5V supply. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/333734 https://www.scopus.com/inward/record.uri?eid=2-s2.0-39749127228&doi=10.1109%2fVLSIC.2007.4342748&partnerID=40&md5=c4fbc7f20bda0d8c991aa225baac681a |
DOI: | 10.1109/VLSIC.2007.4342748 | SDG/Keyword: | CMOS integrated circuits; Data mining; Variable frequency oscillators; Clock/data recovery (CDR); Jitter transfer; Phase detector; Jitter |
Appears in Collections: | 電機工程學系 |
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