https://scholars.lib.ntu.edu.tw/handle/123456789/334022
標題: | An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL | 作者: | Y.-J. Lai TSUNG-HSIEN LIN |
關鍵字: | Calibration; CMOS integrated circuits; Frequency synthesizer; Period-based frequency comparison; Phase detector; Phase-locked loop (PLL); Voltage-controlled oscillator (VCO) | 公開日期: | 二月-2007 | 卷: | 42 | 期: | 2 | 起(迄)頁: | 340-349 | 來源出版物: | IEEE Journal of Solid-State Circuits | 摘要: | This paper reports an agile VCO frequency calibration technique and its application on a 10-GHz CMOS integer-N phase-locked loop. The proposed calibration method accomplishes efficient search for an optimum VCO discrete tuning curve among a group of frequency sub-bands. The agility is attributed to a proposed frequency comparison technique which is based on measuring the period difference between two signals. Other mixed-signal circuits are also developed to facilitate this approach. The PLL incorporating the proposed calibration technique is implemented in a 0.18-μm CMOS process. The measured PLL phase noise at 10 GHz is -102 dBc/Hz at 1-MHz offset frequency and the reference spurs are lower than -48 dBc. The PLL consumes 44 mW in the low-current mode. The calibration time is less than 4 μs. © 2007 IEEE. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/334022 https://www.scopus.com/inward/record.uri?eid=2-s2.0-33847730295&doi=10.1109%2fJSSC.2006.889360&partnerID=40&md5=ac7bbd21c55c024c3156671160b27445 |
ISSN: | 00189200 | DOI: | 10.1109/JSSC.2006.889360 | SDG/關鍵字: | Frequency synthesizer; Period-based frequency comparison; Phase detectors; Acoustic noise; Bandwidth; Calibration; CMOS integrated circuits; Natural frequencies; Phase locked loops; Variable frequency oscillators |
顯示於: | 電子工程學研究所 |
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