|HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy Reduction
|Embedded Systems; Instruction Cache; Low Power Design
|Proceedings of the International Symposium on Low Power Electronics and Design
Power consumption is an important design issue of current embedded systems. It has been shown that the instruction cache accounts for a significant portion of the power dissipation of the whole chip. Several studies propose to add a cache (L0 cache) that is very small relative to the conventional L1 cache on chip for power optimization since a smaller cache has lower load capacitance. However, energy savings often come at the cost of performance degradation. In this paper, we propose a novel instruction cache architecture, the HotSpot cache, that achieves energy savings without sacrificing performance. The HotSpot cache identifies frequently accessed instructions dynamically and stores them in the L0 cache. Other instructions are placed only in the L1 cache. A steering mechanism is employed to direct an instruction to its allocated cache in the instruction fetch stage. The simulation results show that the HotSpot cache can achieve 52% instruction cache energy reduction on the average for a set of multimedia applications without performance degradation. © 2004 ACM.
|Cache memory; Design; Electric power supplies to apparatus; Energy conservation; Low power electronics; Power electronics; Instruction caches; Instruction fetch; Low-power design; Multimedia applications; Performance degradation; Power Optimization; Steering mechanisms; Temporal and spatial; Embedded systems
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