https://scholars.lib.ntu.edu.tw/handle/123456789/499886
標題: | A Subharmonically Injection-Locked All-Digital PLL Without Main Divider | 作者: | Zeng, K.-H. Kuan, T.-K. SHEN-IUAN LIU |
關鍵字: | all-digital phase-locked loop; injection-locked; sub-harmonically | 公開日期: | 2015 | 卷: | 62 | 期: | 11 | 起(迄)頁: | 1033-1037 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A subharmonically injection-locked all-digital phase-locked loop (ADPLL) without a main divider is presented. It achieves not only low power but also low phase noise over the process, voltage, and temperature (PVT) variations. This ADPLL uses only a simple bang-bang phase detector without a time-to-digital converter when both frequency and phase locking. Moreover, the injection pulse can be self-adjusted to optimal timing over the PVT variations without additional calibration loop. This ADPLL is fabricated in a 40-nm CMOS process; it consumes 3.04 mW under a standard supply of 1.1 V excluding output buffers. The measured phase noise of the proposed ADPLL is -121.4 dBc/Hz at 1-MHz offset. The integrated RMS jitter is 109.6 fs for the offset frequency from 1 kHz to 100 MHz. The calculated figure-of-merit is equal to -254.39 dB. © 2015 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/499886 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84946839579&doi=10.1109%2fTCSII.2015.2455292&partnerID=40&md5=5a14ee9bcb258dbbb90761f7c33149a3 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2015.2455292 | SDG/關鍵字: | Frequency converters; Phase locked loops; Phase noise; All digital phase locked loop; Bang-bang phase detectors; Figure of merits; Injection locked; Injection pulse; Offset frequencies; sub-harmonically; Time to digital converters; Phase comparators |
顯示於: | 電機工程學系 |
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