https://scholars.lib.ntu.edu.tw/handle/123456789/559277
標題: | Enhanced power and signal integrity through layout optimization of high-speed memory systems | 作者: | Weng, P.-Y. Cheng, C.-H. Wu, T.-L. Chen, C.-H. Chen, J. Kuo, E. Liao, C.-L. Mutnury, B. TZONG-LIN WU |
公開日期: | 2019 | 卷: | 2019-December | 來源出版物: | IEEE Electrical Design of Advanced Packaging and Systems Symposium | URI: | https://www.scopus.com/inward/record.url?eid=2-s2.0-85085060784&partnerID=40&md5=d2d243d8b127d3b421138f45e788f002 https://scholars.lib.ntu.edu.tw/handle/123456789/559277 |
DOI: | 10.1109/EDAPS47854.2019.9011625 |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。