https://scholars.lib.ntu.edu.tw/handle/123456789/581133
標題: | A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time | 作者: | Qian Y.C Chao Y.-Y SHEN-IUAN LIU |
公開日期: | 2019 | 起(迄)頁: | 95-98 | 來源出版物: | Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 | 摘要: | A sub-sampling phase-locked loop (SSPLL) is presented to tolerate the supply interference and have a short re-locking time. A sampling phase detector, a voltage-to-current converter and a mini-dead zone creator are presented. The low in-band phase noise of the proposed SSPLL is kept and the power penalty is low. This SSPLL is realized in a 0.18μm CMOS process and its active area is 0.097mm2. The power consumption is 13.59mW from a 1.8V supply. At the output frequency of 2.2 GHz, this SSPLL achieves an in-band phase noise of-115.33dBc/Hz at 100kHz offset frequency with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 0.77 ps. ? 2019 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85083643592&doi=10.1109%2fA-SSCC47793.2019.9056927&partnerID=40&md5=f7a266ee520de2cc6e29574a5e6320aa https://scholars.lib.ntu.edu.tw/handle/123456789/581133 |
DOI: | 10.1109/A-SSCC47793.2019.9056927 | SDG/關鍵字: | Locks (fasteners); Phase locked loops; Phase noise; In-band phase noise; Offset frequencies; Output frequency; Power penalty; Robust operation; Root mean square jitter; Sampling phase detector; Voltage-to-current converters; Phase comparators |
顯示於: | 電機工程學系 |
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