https://scholars.lib.ntu.edu.tw/handle/123456789/581136
標題: | A 5-Gb/s Adaptive Digital CDR Circuit with SSC Capability and Enhanced High-Frequency Jitter Tolerance | 作者: | Chang S.-C SHEN-IUAN LIU |
關鍵字: | Clock and data recovery; high-frequency; jitter tolerance; phase interpolator; spread-spectrum clocking | 公開日期: | 2021 | 卷: | 68 | 期: | 1 | 起(迄)頁: | 161-165 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A 5-Gb/s digital clock/data recovery (DCDR) circuit with spread-spectrum clocking (SSC) capability and enhanced high-frequency jitter tolerance (JTOL) is presented. To track input data with both the frequency offset and the SSC, an integral gain controller is used to adjust an integral gain of the digital loop filter. It enhances the high-frequency JTOL. This DCDR circuit is fabricated in 40nm CMOS process. Its active area is 0.022mm2 and the power consumption is 9.9mW from a 1 V supply. With a 5-Gb/s PRBS of 27-1, the measured rms jitter of the retimed data is 9.47ps. For input data with the frequency offset of ±300ppm and SSC of -5000ppm, the measured minimum high-frequency JTOL is equal to 0.55 UIpp by using the proposed integral gain controller with a bit error rate (BER) < 10{-12}. ? 2004-2012 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85098275264&doi=10.1109%2fTCSII.2020.3008777&partnerID=40&md5=6ebced6042bbb3e266b0313a9c8fa0aa https://scholars.lib.ntu.edu.tw/handle/123456789/581136 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2020.3008777 | SDG/關鍵字: | Bit error rate; Clock and data recovery circuits (CDR circuits); Clocks; Frequency allocation; Gain control; Input output programs; Timing circuits; Digital clocks; Digital loop filters; Frequency offsets; High frequency HF; Input datas; Integral gain; Jitter tolerance; Spread spectrum clocking; Jitter |
顯示於: | 電機工程學系 |
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