Browsing by Type "conference paper"

A 10-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented by using the digital place-and-route (DPR) tools. The floorplan and blockage constraint for the bootstrapped switch and the comparator are presented to improve the parasitic capacitances caused by the DPR tools, respectively. The redundancy in the capacitive digital-to-analog converter (CDAC) and the on-chip reference buffer are presented to relieve the CDAC settling error. This calibration-free SAR ADC is fabricated in 40-nm CMOS technology and its active area is 0.0072 mm2. To compare with the full-custom method, the DPR flow has speeded up by a factor of 76 to complete the interconnection wires. Its power dissipation is 418-μ W at 100-MS/s and the calculated Walden FoM is 10.9-fJ/c. step at Nyquist frequency.

In the conventional PLL, the loop filter is composed of passive capacitor which occupies the most parts of chip area. As a result, PLL can save the area by replacing the passive capacitor which stores or releases the charges to a current-controlled oscillator and a dummy oscillator which store the phase information. To reduce the output phase noise, the letter adopts sub-sampling technique. As the loop locks the frequency and the phase difference between reference and divider output is less than 180°, the loop turns off the frequency-locked loop and the sub-sampling phase detector with higher gain dedicates on phase locking. Meanwhile, the loop turns off the divider path so as to avoid the divider from injecting phase noise into the system. However, the sub-sampling technique brings three side effects and lets the reference spur raise up. Hence, this thesis adopts spur reduction technique to alleviate those disadvantages from sub-sampling technique. The proposed PLL is fabricated in TSMC 90nm CMOS technology which active area is 0.02mm2 and provides 2GHz clock. The reference spur is -49.42 dBc and phase noise is -80.32 dBc/Hz at 1MHz offset from carrier frequency under 1.2V power supply with 8.68mW power dissipation.

This paper presents a 0.25μm HV-CMOS implementation of a Synchronous Inversion and Charge Extraction (SICE) interface circuit for piezoelectric energy harvesting. The bias-flip interfacing circuits which perform voltage inversion on the extremes of the voltage waveform have been proved effectively boosting the output power of piezoelectric energy harvesting. The proposed SICE interfacing circuit inverts the piezoelectric voltage on each extremum (bias flip action) for a given number of extremum occurrences, and then extracts the total electrostatic through the Synchronous Electric Charge Extraction (SECE) circuit. Thus, the SICE circuit is a combination of Synchronous Switch Harvesting on Inductor (SSHI) and the SECE circuits. It can achieve high power gain and be independent of loading impedance. The SICE interfacing circuit in TSMC 0.25μm HV-CMOS has been executed and taped-out. The post layout simulation results, including power consumption, circuit efficiency, and power gain will be presented in this paper. © 2018 IEEE.

An energy efficient delta-sigma time-to-digital converter (TDC) is presented in this paper. Compared with conventional circuit techniques, non-ideal effects associated with switching noise and transistor leakage can be generally prevented due to the use of a gated-free ring oscillator and leakage-suppression switches in the circuit implementation. The proposed TDC is fabricated in 90-nm CMOS, consuming a current of 5 μA from a 0.3-V supply. With first-order shaping of the quantization noise, the circuit demonstrates an equivalent number of bits (ENOB) of 10.9 bits in 50-kHz signal bandwidth. © 2017 IEEE.

A small-area energy-efficient true random number generator (TRNG) is presented. This TRNG introduces a jitter signal generator to realize the noise pre-amplification, and utilizes a metastable latch to resolve the jitter edges. Moreover, to tolerate the process and environment variations, an offset calibration is employed to dynamically correct the bias of the probability of logic 0/1 in background. A prototype is fabricated in 40-nm CMOS technology. It occupies an area of 0.0014mm2 and consumes 214nW from a 0.8-V supply at a throughput of 500kbps. The proposed TRNG passes the NIST tests, and its calculated FOM is 0.43pJ/bit. © 2014 IEEE.

A 0.5-V 10-Mbps differential BPSK (D-BPSK) transceiver is presented in this paper. The receiver (RX) adopts a dynamic phase-to-amplitude conversion with the injection-locking technique to demodulate the received signal. The transmitter (TX) multiplexes the appropriate phases to generate the phase-modulation signal using subharmonic injection technique. This work is fabricated in TSMC 180-nm CMOS process. At 10-Mbps data rate, the RX and TX consume 0.29 mW and 1 mW, respectively. The energy efficiency of RX and TX achieves 100 pJ/bit and 29 pJ/bit, respectively. RX sensitivity is -60 dBm. © 2018 IEEE.

This paper presents the design of a low-power wake-up receiver (WuRX). The proposed WuRX composed of an active envelope detector with high input impedance to support high passive gain, a self-biased high-gain IF-Amplifier, a dynamic comparator, and a proposed level-Tracking calibration circuit that mitigates circuit drift. This OOK-modulated WuRX is implemented in a 90-nm CMOS process and operates at the 400-MHz MICS band. Operated from a 0.5-V supply, this WuRX consumes 1.79-W. It supports 250-kbps data rate and achieves-40-dBm sensitivity. ? 2020 IEEE.

A Y-vector oscillator network is devised to configure (sub)-mm-wave/terahertz (THz) beamforming systems with minimized footprint and energy consumption. It requires no traditional adjustable phase shifter at multi-channel front end which usually suffer from high insertion loss at these frequencies. A compact (1.4mm2) CMOS lx4 Beam Steering Phased Array (BSPA) based on this network is validated at 0.55THz with pm 30 steering angle range. This is the first monolithic BSPA reported beyond 0.5THz. © 2018 IEEE.