公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2013 | Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assembly | Kuo, Y.-H.; Liu, C.-S.; Li, Y.-C.; Lu, Y.-C.; YI-CHANG LU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings | 1 | 0 | |
2007 | Performance benefits of monolithically stacked 3-D FPGA | Lin, Mingjie; El Gamal, Abbas; YI-CHANG LU ; Wong, Simon | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 119 | 88 | |
2006 | Performance benefits of monolithically stacked 3D-FPGA | Lin, Mingjie; El Gamal, Abbas; Lu, Yi-Chang; Wong, Simon; YI-CHANG LU | Internation symposium on Field programmable gate arrays - FPGA? 06 | 66 | 0 | |
2014 | A pixel-based depth estimation algorithm and its hardware implementation for 4-D light field data | Chang, C.-W.; Chen, M.-R.; Hsu, P.-H.; Lu, Y.-C.; YI-CHANG LU | Proceedings - IEEE International Symposium on Circuits and Systems | 10 | 0 | |
2013 | Power distribution network modeling for 3-D ICs with TSV arrays | Shen, C.-K.; Lu, Y.-C.; Chiou, Y.-P.; Cheng, T.-Y.; Wu, T.-L.; YI-CHANG LU ; TZONG-LIN WU ; YIH-PENG CHIOU | Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | 0 | |
2015 | Power efficient special processor design for Burrows-Wheeler-transform-based short read sequence alignment | Nae-Chyun Chen; Tai-Yin Chiu; Yu-Cheng Li; Yu-Chun Chien; Yi-Chang Lu; YI-CHANG LU | IEEE International Biomedical Circuits and Systems Conference | 2 | 0 | |
2021 | Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup | Yu C.-C; Hu Y.H; Lu Y.-C; Chen C.C.-P.; YI-CHANG LU | Proceedings -Design, Automation and Test in Europe, DATE | 0 | 0 | |
2013 | A power-efficient asynchronous circuit style with selective input-channel restoring | Tang, C.-K.; Lu, Y.-C.; YI-CHANG LU | Midwest Symposium on Circuits and Systems | 0 | 0 | |
2015 | A prediction method of heat generation in the silicon substrate for 3-D ICs | Yi-An Hsu; Chi-Hsuan Cheng; Yi-Chang Lu; Tzong-Lin Wu; YI-CHANG LU | IEEE Conference on Electrical Performance of Electronic Packaging and Systems | 0 | 0 | |
2016 | Queue-based segmentation algorithm for refining depth maps in light field camera applications | Yi-Hsiang Chen; Nae-Chyun Chen; Yu-Hsiang Kao; Yu-Cheng Li; Yi-Chang Lu; YI-CHANG LU | IEEE Global Conference on Consumer Electronics | 1 | 0 | |
2021 | A Real Time Video Stabilizer Based on Feature Trajectories and Global Mesh Warping | Huang S.-J; Lin Y.-H; Weng C.-H; YI-CHANG LU | 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021 | 0 | 0 | |
2021 | RGB-NIR Demosaicking Using a Two-Phase Primal-Dual Algorithm with a Laplacian Guided Image Filter Prior | Duh W.-Y; Lin Y.-H; Lu Y.-C.; YI-CHANG LU | 2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021 | 0 | 0 | |
2022 | Shadow Removal Through Learning-Based Region Matching and Mapping Function Optimization | Hsieh, Shih Wei; Yang, Chih Hsiang; YI-CHANG LU | Proceedings - IEEE International Conference on Multimedia and Expo | 1 | 0 | |
2010 | Signal/Power integrity modeling of high-speed memory modules using chip-package-board co-analysis | YI-CHANG LU ; TZONG-LIN WU ; HSIN-SHU CHEN ; RUEY-BEEI WU | IEEE Transactions on Electromagnetic Compatibility | | 24 | |
2016 | A special processor design for nucleotide basic local alignment search tool with a new banded two-hit method | Chih-Yu Chang; Yu-Cheng Li; Nae-Chyun Chen; Xiao-Xuan Huang; Yi-Chang Lu; YI-CHANG LU | IEEE Nordic Circuits and Systems Conference | 2 | 0 | |
2019 | A special-purpose processor for FFT-based digital refocusing using 4-D light field data | Chen, M.-R.; Liu, H.-W.; Lin, Y.-H.; Lu, Y.-C.; YI-CHANG LU | Proceedings - IEEE International Symposium on Circuits and Systems | 1 | 0 | |
2016 | Step Shift: a fast image segmentation algorithm and its hardware implementation for next-generation-sequencing fluorescence data | Xiao-Xuan Huang; Chun-Hsien Ho; Yu-Cheng Li; Nae-Chyun Chen; Yi-Chang Lu; YI-CHANG LU | IEEE Asia Pacific Conference on Circuits and Systems | 0 | 0 | |
2018 | Subpixel-level-accurate algorithm for removing double-layered reflections from a single image | Shih-Wei Hsieh; Yao-Cheng Yang; Chi-Ming Yeh; Sheng-Jui Huang; Yi-Chang Lu; YI-CHANG LU | IEEE International Conference on Image Processing | 1 | 0 | |
2013 | Test generation of path delay faults induced by defects in power TSV | Shih, C.-J.; Hsieh, S.-A.; Lu, Y.-C.; Li, J.C.-M.; Wu, T.-L.; TZONG-LIN WU ; YI-CHANG LU ; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 2 | 0 | |
2014 | Testing of TSV-induced small delay faults for 3-D integrated circuits | Chun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; James C.-M. Li; Krishnendu Chakrabarty; YI-CHANG LU ; CHIEN-MO LI | IEEE Trans. Very Large Scale Integration (VLSI) Systems | 17 | 13 | |