公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2018 | The impact of 2016 guideline on clinical practice for the management of hospital-acquired and ventilator-associated pneumonia in Taiwan | Yang, Chia-Lin; Chen, Yen-Fu; Lin, Chi-Ying; CHIA-LIN YANG | European Respiratory Journal | | | |
2019 | The impact of emerging technologies on architectures and system-level management: Invited paper | Henkel, J.; Hu, X.S.; Cheng, H.-Y.; Yang, C.-L.; Amrouch, H.; Rapp, M.; Salamin, S.; Reis, D.; Gao, D.; Yin, X.; Niemier, M.; Zhuo, C.; CHIA-LIN YANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
2023 | Impact of Non-Volatile Memory Cells on Spiking Neural Network Annealing Machine With In-Situ Synapse Processing | Wei, Ming Liang; Yayla, Mikail; Ho, Shu Yin; Chen, Jian Jia; Amrouch, Hussam; CHIA-LIN YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | 0 | 0 | |
2015 | Improving DRAM latency with dynamic asymmetric subarray | Lu, S.-L.; Lin, Y.-C.; CHIA-LIN YANG | Annual International Symposium on Microarchitecture | 37 | 0 | |
2017 | Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling | Chen, Li-Jhan; Cheng, Hsiang-Yun; Wang, Po-Han; CHIA-LIN YANG | Ieee Computer Architecture Letters | | | |
2016 | Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality | Liu, R.-S.; Chuang, M.-Y.; Yang, C.-L.; Li, C.-H.; Ho, K.-C.; Li, H.-P.; CHIA-LIN YANG | IEEE Transactions on Computers | | | |
2004 | An Interrupt-Emulation Mechanism with Power-Saving for Flash-Memory Storage Systems | Wu, Chin-Hsien; Kuo, Tei-Wei ; Yang, Chia-Lin | IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis | | | |
2019 | Iotbench: A Benchmark Suite for Intelligent Internet of Things Edge Devices | Lee, C.-I.; Lin, M.-Y.; Yang, C.-L.; Chen, Y.-K.; CHIA-LIN YANG | Proceedings - International Conference on Image Processing, ICIP | | | |
2005 | Joint exploration of architectural and physical design spaces with thermal consideration | CHIA-LIN YANG ; Wu, Y.-W.; Yang, C.-L.; Yuh, P.-H.; Chang, Y.-W.; CHIA-LIN YANG | International Symposium on Low Power Electronics and Design | | | |
2005 | Joint exploration of architectural and physical design spaces with thermal consideration. | Wu, Yen-Wei; Yang, Chia-Lin; Yuh, Ping-Hung; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005 | 18 | 0 | |
2016 | Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture | Wang, P.-H.; Li, C.-H.; CHIA-LIN YANG | Proceedings - Design Automation Conference | 13 | 0 | |
2020 | Lattice: An ADC/DAC-less ReRAM-based processing-in-memory architecture for accelerating deep convolution neural networks | Zheng, Q.; Wang, Z.; Feng, Z.; Yan, B.; Cai, Y.; Huang, R.; Chen, Y.; Yang, C.-L.; Li, H.H.; CHIA-LIN YANG | Proceedings - Design Automation Conference | | | |
2009 | Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs | CHIA-LIN YANG ; Yuh, P.-H.; Yang, C.-L.; Li, C.-F.; Lin, C.-H.; CHIA-LIN YANG | ACM Transactions on Design Automation of Electronic Systems | | | |
2017 | Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach | Lai, C.-H.; Zhao, J.; CHIA-LIN YANG | Proceedings - Design Automation Conference | 11 | 0 | |
2016 | MCSSim: A memory channel storage simulator | Chen, R.; Shao, Z.; Yang, C.-L.; CHIA-LIN YANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | 0 | |
2010 | Memory latency reduction via thread throttling | Cheng, H.-Y.; Lin, C.-H.; Li, J.; CHIA-LIN YANG | Annual International Symposium on Microarchitecture | 37 | 0 | |
2016 | Message from the general chairs | Hsu, W.C.; CHIA-LIN YANG ; WEI-CHUNG HSU | Proceedings of the Annual International Symposium on Microarchitecture, MICRO | 0 | 0 | |
2017 | Message from the general co-chairs | Garrett, D.; CHIA-LIN YANG | Proceedings of the International Symposium on Low Power Electronics and Design | 0 | 0 | |
2016 | Message from the Program Co-Chairs | Yang, C.-L.; Garrett, D.; CHIA-LIN YANG | Proceedings of the International Symposium on Low Power Electronics and Design | | | |
2009 | A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking | Wang, Sung-Wen; Yang, Shu-Sian; Chen, Hong-Ming; Yang, Chia-Lin ; Wu, Ja-Ling | Journal of Signal Processing Systems | | | |